Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
first-word fall-through/serial in (FWFT/SI)
FWFT/SI is a dual-purpose pin. During master reset, the state of the FWFT/SI input determines whether the
device operates in FWFT mode or standard mode.
If, at the time of master reset, FWFT/SI is high, FWFT mode is selected. This mode uses OR
to indicate whether
there is valid data at the data outputs (Qn). It also uses IR
to indicate whether the FIFO memory has any free
space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK
rising edges; REN
= low is not necessary. Subsequent words must be accessed using REN and RCLK.
If, at the time of master reset, FWFT/SI is low, standard mode is selected. This mode uses EF
to indicate whether
there are any words present in the FIFO memory. It also uses the FF
to indicate whether the FIFO memory has
any free space for writing. In standard mode, every word read from the FIFO, including the first, must be
requested using REN
and RCLK.
After master reset, FWFT/SI acts as a serial input for loading PAE
and PAF offsets into the programmable
registers. The serial input function can be used only when the serial loading method is selected during master
reset. Serial programming using the FWFT/SI pin functions the same way in both FWFT and standard modes.
write clock (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met, with
respect to the low-to-high transition of WCLK. It is permissible to stop WCLK. Note that while WCLK is idle, the
FF
/IR, PAF, and HF flags are not updated. (WCLK is capable only of updating the HF flag to low.) The write and
read clocks can be either independent or coincident.
write enable (WEN
)
When WEN
is low, data can be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the
device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.
When WEN
is high, no new data is written in the RAM array on each WCLK cycle.
To prevent data overflow in the FWFT mode, IR
goes high, inhibiting further write operations. After completion
of a valid read cycle, IR
goes low, allowing a write to occur. The IR flag is updated by two WCLK cycles + t
sk
after the valid RCLK cycle.
To prevent data overflow in the standard mode, FF
goes low, inhibiting further write operations. After completion
of a valid read cycle, FF
goes high, allowing a write to occur. The FF is updated by two WCLK cycles + t
sk
after
the RCLK cycle.
WEN
is ignored when the FIFO is full in either FWFT or standard modes.
read clock (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge
of the RCLK input. It is permissible to stop RCLK. While RCLK is idle, the EF
/OR, PAE and HF flags are not
updated. RCLK is capable only of updating the HF
flag to high. The write and read clocks can be independent
or coincident.