Datasheet
www.ti.com
APPLICATION INFORMATION
150 Ω
Open-Drain
CPU Interface
Motherboard
Interface
V
REF
(1)
= 1.5 V
GATE
(1)
B1 (V
BIAS
)
(1)
TVC3306
(1) V
REF
and V
BIAS
can be applied to any one of the pass transistors. GATE must be connected externally to V
BIAS
.
B3
8 7 6 5
1 2 3 4
150 Ω200 kΩ
B2
V
DDREF
= 3.3 V V
DPU
= 2.5 V
A3A2A1
Application Operating Conditions
SN74TVC3306
DUAL VOLTAGE CLAMP
SCDS112C – MARCH 2001 – REVISED MARCH 2005
Figure 2. Typical Application Circuit
For the clamping configuration, the common GATE input must be connected to one side (An or Bn) of any one of
the pass transistors, making that the V
BIAS
connection of the reference transistor and the opposite side (Bn or
An) the V
REF
connection. When V
BIAS
is connected through a 200-k Ω resistor to a 3-V to 5.5-V V
CC
supply and
V
REF
is set to 0 V to V
CC
– 0.6 V, the output of each switch has a maximum clamp voltage equal to V
REF
. A filter
capacitor on V
BIAS
is recommended.
see Figure 2
MIN TYP
(1)
MAX UNIT
V
BIAS
BIAS voltage V
REF
+ 0.6 2.1 5 V
V
GATE
GATE voltage V
REF
+ 0.6 2.1 5 V
V
REF
Reference voltage 0 1.5 4.4 V
V
DPU
Drain pullup voltage 2.36 2.5 2.64 V
I
PASS
Pass-transistor current 14 mA
I
REF
Reference-transistor current 5 µ A
T
A
Operating free-air temperature –40 85 °C
(1) All typical values are at T
A
= 25°C.
5