Datasheet

SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
TVC voltage-limiting application
For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any
one of the transistors (see Figure 3). This connection determines the V
BIAS
input of the reference transistor. The
V
BIAS
input is connected through a pullup resistor (typically, 200 kΩ ) to the V
DD
supply. A filter capacitor on V
BIAS
is recommended. The opposite side of the reference transistor is used as the reference voltage (V
REF
)
connection. The V
REF
input must be less than V
DDREF
– 1 V to bias the reference transistor into conduction.
The reference transistor regulates the gate voltage (V
GATE
) of all the pass transistors. V
GATE
is determined by
the characteristic gate-to-source voltage difference (V
GS
) because V
GATE
= V
REF
+ V
GS
. The low-voltage side
of the pass transistors has a high-level voltage limited to a maximum of V
GATE
– V
GS
, or V
REF
.
200 kΩ
V
DDREF
= 3.3 V
150 Ω 150 Ω 150 Ω 150 Ω
Open-Drain
CPU Interface
Motherboard
Interface
3
A2
4
A3
5
A4
12
A11
1
V
DPU
TVC3010
GATE
†
24
B1 (V
BIAS
)
†
23
2
A1 (V
REF
)
†
†
V
REF
and V
BIAS
can be applied to any one of the pass transistors. GATE must be connected externally to V
BIAS
.
B2
22
B3
21
B4
20
B11
13
Figure 3. Typical Application Circuit