Datasheet

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SN74TVC3010

10-BIT VOLTAGE CLAMP

SCDS088G – APRIL 1999 – REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Designed to be Used in Voltage-Limiting

Applications

6.5-Ω On-State Connection Between Ports

A and B

Flow-Through Pinout for Ease of Printed

Circuit Board Trace Routing

Direct Interface With GTL+ Levels

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

description/ordering information

The SN74TVC3010 provides 11 parallel NMOS

pass transistors with a common gate. The low

on-state resistance of the switch allows

connections to be made with minimal propagation

delay.

The device can be used as a 10-bit switch with the gates cascaded together to a reference transistor. The

low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to

protect components with inputs that are sensitive to high-state voltage-level overshoots. (See Application

Information in this data sheet.)

All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can

be used as the reference transistor. Since, within the device, the characteristics from transistor to transistor are

equal, the maximum output high-state voltage (V

) is approximately the reference voltage (V

REF

), with

minimal deviation from one output to another. This is a large benefit of the TVC solution over discrete devices.

Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the

low-voltage side, and the I/O signals are bidirectional through each FET.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

–40 C to 85 C

SOIC – DW

Tube SN74TVC3010DW

TVC3010

–40 C to 85 C

SOIC – DW

Tape and reel SN74TVC3010DWR

TVC3010

–40

C to 85

SSOP (QSOP) – DBQ Tape and reel SN74TVC3010DBQR TVC3010

TSSOP – PW Tape and reel SN74TVC3010PWR TT010

TVSOP – DGV Tape and reel SN74TVC3010DGVR TT010

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

GND

A10

A11

GATE

B10

B11

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (21 pages)

PAGE 1
SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 D D D D D DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) Designed to be Used in Voltage-Limiting Applications 6.
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SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 simplified schematic GATE B1 B2 B3 B4 B11 24 23 22 21 20 13 1 2 3 4 5 12 GND A1 A2 A3 A4 A11 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input/output voltage range, VI/O (see Note 1) . . . . . . . . . . . . . .
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SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 application operating conditions (see Figure 3) VBIAS VGATE BIAS voltage VREF VDPU Reference voltage IPASS IREF Pass-transistor current TA Operating free-air temperature GATE voltage Drain pullup voltage MIN TYP MAX VREF + 0.6 VREF + 0.6 2.1 5 UNIT V 2.1 5 V 0 1.5 4.4 V 2.36 2.5 2.
PAGE 4
SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VDPU 3.3 V Motherboard Interface 200 kΩ † GATE 24 RDPU = 150 Ω RDPU = 150 Ω † RDPU = 150 Ω † † RDPU = 150 Ω B1 (VBIAS) 23 B2 22 B3 21 B4 20 B11 13 2 A1 (VREF) 3 A2 (VS) 4 A3 (VS) 5 A4 (VS) 12 A11 (VS) ‡ TVC3010 1 § § § § Open-Drain Test Interface TESTER CALIBRATION SETUP (see Note C) GATE 2.5 V Input Tester 1.25 V 1.
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SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 APPLICATION INFORMATION TVC background information In personal computer (PC) architecture, there are industry-accepted bus standards. These standards define, among other things, the I/O voltage levels at which the bus communicates. Examples include the GTL+ host bus, the AGP graphics port, and the PCI local bus. In new designs, the system components must communicate with existing bus infrastructure.
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SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 APPLICATION INFORMATION TVC voltage-limiting application For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any one of the transistors (see Figure 3). This connection determines the VBIAS input of the reference transistor. The VBIAS input is connected through a pullup resistor (typically, 200 kΩ ) to the VDD supply. A filter capacitor on VBIAS is recommended.
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SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 APPLICATION INFORMATION electrical characteristics The electrical characteristics of the NMOS transistors used in the TVC devices are illustrated by TI SPICE simulations. Figure 4 shows the test configuration for the TI SPICE simulations. The results, shown in Figures 5 and 6, show the current through a pass transistor versus the voltage at the source for different reference voltages.
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SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 I PASS – Pass Current – mA APPLICATION INFORMATION VREF = 1 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS – Pass Current – mA VSPASS – Low Reference Voltage – V VREF = 1.5 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.
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SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 I PASS – Pass Current – mA APPLICATION INFORMATION VREF = 2.5 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS – Pass Current – mA VSPASS – Low Reference Voltage – V VREF = 2.5 V VDDREF = 4 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.
PAGE 10
SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088G – APRIL 1999 – REVISED AUGUST 2003 APPLICATION INFORMATION features and benefits The TVC family has several features that benefit a system designer when implementing a sensitive-I/O-protection solution. Table 1 lists these features and their associated benefits. Table 1. Features and Benefits FEATURES BENEFITS Any FET can be used as the reference transistor.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device SN74TVC3010PWRG4 16-Aug-2012 Status (1) ACTIVE Package Type Package Drawing TSSOP PW Pins 24 Package Qty 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.0 2.1 8.0 16.0 Q1 SN74TVC3010DBQR SSOP DBQ 24 2500 330.0 16.4 SN74TVC3010DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74TVC3010DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74TVC3010DBQR SSOP DBQ 24 2500 367.0 367.0 38.0 SN74TVC3010DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74TVC3010DWR SOIC DW 24 2000 367.0 367.0 45.0 SN74TVC3010PWR TSSOP PW 24 2000 367.0 367.0 38.
PAGE 15
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.