Datasheet

SN54LVTH18646A, SN54LVTH182646A, SN74LVTH18646A, SN74LVTH182646A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS311D – MARCH 1994 – REVISED JUNE 1997
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (normal mode) (see Figure 15)
SN54LVTH182646A SN74LVTH182646A
V
CC
= 3.3 V
± 0.3 V
V
CC
= 2.7 V
V
CC
= 3.3 V
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency CLKAB or CLKBA 0 120 0 100 0 120 0 100 MHz
t
w
Pulse duration CLKAB or CLKBA high or low 3.8 5 3.8 5 ns
t
su
Setup time
A before CLKAB↑ or
B before CLKBA↑
2.9 3.1 2.9 3.1 ns
t
h
Hold time
A after CLKAB↑ or
B after CLKBA↑
0.8 0.2 0.8 0.2 ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (test mode) (see Figure 15)
SN54LVTH182646A SN74LVTH182646A
V
CC
= 3.3 V
± 0.3 V
V
CC
= 2.7 V
V
CC
= 3.3 V
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency TCK 0 50 0 40 0 50 0 40 MHz
t
w
Pulse duration TCK high or low 9.5 10.5 9.5 10.5 ns
t
St ti
A, B, CLK, DIR, OE or S
before TCK↑
6.5 7 6.5 7
t
su
Setup time
TDI before TCK↑
2.5 3.5 2.5 3.5
ns
TMS before TCK↑ 2.5 3.5 2.5 3.5
t
Hldti
A, B, CLK, DIR, OE or S
after TCK↑
1.5 1 1.5 1
t
h
Hold time
TDI after TCK↑
1.5 1 1.5 1
ns
TMS after TCK↑ 1.5 1 1.5 1
t
d
Delay time Power up to TCK↑ 50 50 50 50 ns
t
r
Rise time V
CC
power up 1 1 1 1 µs
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.