Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74LVTH TSSOP 64

SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514

3.3-V ABT SCAN TEST DEVICES

WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS670C – AUGUST 1996 – REVISED MARCH 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments (TI)

SCOPE

 Family of Testability Products

Members of the TI

Widebus

 Family

State-of-the-Art 3.3-V ABT Design Supports

Mixed-Mode Signal Operation (5-V Input

and Output Voltages With 3.3-V V

)

Support Unregulated Battery Operation

Down to 2.7 V

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

B-Port Outputs of ’LVTH182514 Devices

Have Equivalent 25-Ω Series Resistors, So

No External Resistors Are Required

Compatible With the IEEE Std 1149.1-1990

(JTAG) Test Access Port and

Boundary-Scan Architecture

SCOPE

 Instruction Set

– IEEE Std 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

Package Options Include 64-Pin Plastic

Thin Shrink Small-Outline (DGG) and 64-Pin

Ceramic Dual Flat (HKC) Packages Using

0.5-mm Center-to-Center Spacings

description

The ’LVTH18514 and ’LVTH182514 scan test devices with 20-bit universal bus transceivers are members of

the TI SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990

boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is

accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) V

operation, but with the

capability to provide a TTL interface to a 5-V system environment.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

SCOPE, Widebus, UBT, and TI are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LVTH18514, SN54LVTH182514 . . . HKC PACKAGE

SN74LVTH18514, SN74LVTH182514 . . . DGG PACKAGE

(TOP VIEW)

LEBA

OEBA

GND

A10

A11

A12

A13

GND

A14

A15

A16

A17

A18

A19

GND

A20

CLKENAB

CLKAB

TDO

TMS

CLKBA

CLKENBA

GND

B10

B11

B12

B13

GND

B14

B15

B16

B17

B18

B19

GND

B20

OEAB

LEAB

TDI

TCK

Summary of content (36 pages)

PAGE 1
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 D D D D D D D D D D Members of the Texas Instruments (TI) SCOPE  Family of Testability Products Members of the TI Widebus  Family State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.
PAGE 2
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 description (continued) In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes.
PAGE 3
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.
PAGE 4
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 Terminal Functions TERMINAL NAME 4 DESCRIPTION A1–A20 Normal-function A-bus I/O ports. See function table for normal-mode logic. B1–B20 Normal-function B-bus I/O ports. See function table for normal-mode logic. CLKAB, CLKBA Normal-function clock inputs. See function table for normal-mode logic.
PAGE 5
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 test architecture Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Std 1149.1-1990. Test instructions, test data, and test control signals are passed along this serial-test bus. The TAP controller monitors two signals from the test bus: TCK and TMS.
PAGE 6
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 state diagram description The TAP controller is a synchronous finite-state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Std 1149.1-1990. The TAP controller proceeds through its states, based on the level of TMS at the rising edge of TCK.
PAGE 7
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 Shift-DR Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO. On the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register.
PAGE 8
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 register overview With the exception of the bypass and device-identification registers, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that they contain only a shift register.
PAGE 9
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 data register description boundary-scan register The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and output data).
PAGE 10
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 boundary-control register The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run (RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA, and binary count up (COUNT).
PAGE 11
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 device-identification register The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer, part number, and version of this device.
PAGE 12
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 instruction-register opcode description The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction. Table 3.
PAGE 13
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 bypass scan This instruction conforms to the IEEE Std 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode. control boundary to high impedance This instruction conforms to the IEEE Std 1149.
PAGE 14
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 boundary-control register opcode description The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state.
PAGE 15
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 pseudo-random pattern generation (PRPG) A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each falling edge of TCK.
PAGE 16
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.
PAGE 17
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 parallel-signature analysis (PSA) Data appearing at the selected device input-mode I/O pins is compressed into a 40-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK.
PAGE 18
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.
PAGE 19
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 simultaneous PSA and PRPG (PSA/PRPG) Data appearing at the selected device input-mode I/O pins is compressed into a 20-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK.
PAGE 20
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.
PAGE 21
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 simultaneous PSA and binary count up (PSA/COUNT) Data appearing at the selected device input-mode I/O pins is compressed into a 20-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK.
PAGE 22
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.
PAGE 23
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 timing description All test operations of the ’LVTH18514 and ’LVTH182514 are synchronous to the TCK signal. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK.
PAGE 24
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.
PAGE 25
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 recommended operating conditions (see Note 4) SN54LVTH18514 SN74LVTH18514 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 Input voltage 5.5 5.
PAGE 26
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = –3 mA IOH = –8 mA VCC = 3 V IOH = –24 mA IOH = –32 mA VOH VCC = 2 2.7 7V VOL VCC = 3 V VCC = 3.6 V, VCC = 0 or 3.
PAGE 27
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN54LVTH18514 VCC = 3.3 V ± 0.3 V fclock tw Clock frequency Pulse duration CLKAB or CLKBA CLKAB or CLKBA high or low Setup time Hold time 0 100 MIN MAX 0 80 MIN MAX 0 100 VCC = 2.
PAGE 28
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN54LVTH18514 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.
PAGE 29
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 recommended operating conditions (see Note 4) SN54LVTH182514 SN74LVTH182514 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.
PAGE 30
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = –3 mA IOH = –8 mA VOH VCC = 3 V 7V VCC = 2 2.7 VOL VCC = 3 V VCC = 3.6 V, VCC = 0 or 3.
PAGE 31
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN54LVTH182514 VCC = 3.3 V ± 0.3 V fclock tw Clock frequency Pulse duration CLKAB or CLKBA CLKAB or CLKBA high or low th Setup time H ld time ti Hold MAX 0 100 VCC = 2.
PAGE 32
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN54LVTH182514 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.
PAGE 33
SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT 2.7 V 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 2.7 V 1.5 V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 0V tPHL 1.
PAGE 34
PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVTH18514DGGRE4 ACTIVE TSSOP DGG 64 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74LVTH18514DGGR ACTIVE TSSOP DGG 64 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 35
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 36
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.