Datasheet

SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS668C − JULY 1996 − REVISED JUNE 2004
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs of ’LVTH182502A, which are designed to source or sink up to 12 mA, include 25-Ω series
resistors to reduce overshoot and undershoot.
The SN54LVTH18502A and SN54LVTH182502A are characterized for operation over the full military
temperature range of −55°C to 125°C. The SN74LVTH18502A and SN74LVTH182502A are characterized for
operation from −40°C to 85°C.
1B4
1B5
1B6
GND
1B7
1B8
1B9
V
CC
NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
NC
V
CC
2A1
2A2
2A3
GND
2A4
2A5
2A6
V NC TMS 1CLKBA 1A2 1A1 1OEAB GND 1LEAB 1CLKAB TDO
NC
TCK
2CLKBA
2LEBA
2A9
GND
2OEAB
2LEAB
2CLKAB
TDI
2A7 2A8
1LEBA 1O1OEBA
GND
2OEBA
2B9 2B8
GND 1B1 1B2 1B3
SN54LVTH18502A, SN54LVTH182502A . . . HV PACKAGE
(TOP VIEW)
CC
V
CC
NC − No internal connection
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
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15
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17
18
19
20
21
22
23
24
25
26
28 29 30 31 32 33 34
8765493168672
35 36 37 38 39
66 65
27
64 63 62 61
40 41 42 43