Datasheet

SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686A – APRIL 1997 – REVISED DECEMBER 1999
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 24)
SN54LVT8996
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= 3.3 V
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN MAX MIN MAX
f
max
PTCK 25 20 MHz
t
PLH
BYP↑
CON
1 8.7 1 10
ns
t
PHL
BYP↓
CON
1 10 1 11.6
ns
t
PLH
BYP↓
STMS
2.5 12.6 2.5 15.4
ns
t
PHL
BYP↓
STMS
2.5 12.1 2.5 13.9
ns
t
PLH
PTCK
STCK
1 10.2 1 11.8
ns
t
PHL
PTCK
STCK
1 10.5 1 12.2
ns
t
PLH
PTCK↓
CON
3.5 22 3.5 26.4
ns
t
PHL
PTCK↓
CON
3.5 24.6 3.5 28.8
ns
t
PLH
PTCK
↓
PTDO
3 15.5 3 18.3
ns
t
PHL
(shadow-protocol acknowledge)
PTDO
3 15.7 3 18.4
ns
t
PLH
†
PTCK
↓
STMS
5.5 20.1 5.5 25.1
ns
t
PHL
†
(connect)
STMS
5.5 20.3 5.5 24.2
ns
t
PLH
PTDI
STDO
1 8.8 1 10.3
ns
t
PHL
PTDI
STDO
1 9 1 10.6
ns
t
PLH
PTMS
STMS
1 8.9 1 10.3
ns
t
PHL
PTMS
STMS
1 9.1 1 10.6
ns
t
PLH
PTRST
STRST
1 8.7 1 10.2
ns
t
PHL
PTRST
STRST
1 9 1 10.5
ns
t
PLH
PTRST↓
CON 3.5 25.9 3.5 31.1
ns
t
PLH
PTRST↓
STMS 2.5 14.1 2.5 18.3
ns
t
PLH
STDI
PTDO
1 7.3 1 8.5
ns
t
PHL
STDI
PTDO
1 7.9 1 9.3
ns
†
The transitions at STMS are possible only when a shadow-protocol select is issued while STMS is held (in the OFF status) at a level that differs
from that at PTMS. Such operation is not recommended since state synchronization of the primary TAP to secondary TAP cannot be ensured.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.