Datasheet

SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686A – APRIL 1997 – REVISED DECEMBER 1999
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 24)
SN54LVT8996 SN74LVT8996
UNIT
MIN MAX MIN MAX
UNIT
f
lk
Clock frequency
PTCK
V
CC
= 2.7 V 20 20
MHz
f
clock
Clock
freq
u
enc
y
PTCK
V
CC
= 3.3 V ± 0.3V 25 25
MH
z
BYP low
†
8 8
t
Pulse duration
PTCK high 20 20
ns
t
w
P
u
lse
d
u
ration
PTCK low 12 12
ns
PTRST low 9 9
A9–A0 before PTCK↓
‡
10.2 10.2
t
Setu
p
time
PTDI before PTCK↑ 10.1 10.1
ns
t
su
Set
u
p
time
PTMS before BYP↑
†
4 4
ns
PTMS before PTCK↑ 10 10
A9–A0 after PTCK↓
‡
4 4
t
h
Hold time
PTDI after PTCK↑ 4 4
ns
t
h
Hold
time
PTMS after BYP↑
†
4 4
ns
PTMS after PTCK↑ 4 4
†
In normal application of the ASP, such timing requirements with respect to BYP are met implicitly and, therefore, need not be considered.
‡
These requirements apply only in the case in which the address inputs are changed during a shadow protocol. For normal application of the ASP,
it is recommended that the address inputs remain static throughout any shadow protocols. In such cases, the timing of address inputs relative
to PTCK need not be considered.
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design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.