Datasheet

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1A 1Y
1 6
2A 2Y
3 4
SN74LVC2G04-EP
DUAL INVERTER GATE
SGLS365 – AUGUST 2006
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
NanoStar™ – WCSP (DSBGA)
SN74LVC2G04MYEAREP
(3)
0,17-mm Small Bump – YEA
NanoFree™ – WCSP (DSBGA)
0,17-mm Small Bump – YZA SN74LVC2G04MYZAREP
(3)
(Pb-free)
Reel of 3000
NanoStar™ – WCSP (DSBGA)
SN74LVC2G04MYEPREP
(3)
–55 ° C to
0,23-mm Large Bump – YEP
125 ° C
NanoFree™ – WCSP (DSBGA)
0,23-mm Large Bump – YZP SN74LVC2G04MYZPREP
(3)
(Pb-free)
SOT (SOT-23) – DBV Reel of 3000 SN74LVC2G04MDBVREP
(3)
SOT (SC-70) – DCK Reel of 3000 SN74LVC2G04MDCKREP BUG
SOT (SOT-563) – DRL Reel of 4000 SN74LVC2G04MDRLREP
(3)
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
(3) Product Preview
FUNCTION TABLE
(EACH INVERTER)
INPUT OUTPUT
A Y
H L
L H
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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