Datasheet

B
DIR
5
4
A
3
V
CCA
V
CCB
SN74LVC1T45
SCES515K –DECEMBER 2003 –REVISED DECEMBER 2014 www.ti.com
9 Detailed Description
9.1 Overview
The SN74LVC1T45 is single-bit, dual-supply, non-inverting voltage level translation. Pin A and that direction
control pin (DIR) are supported by V
CCA
and pin B is supported by V
CCB
. The A port is able to accept I/O voltages
ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The high on the DIR
allows data transmissions from A to B and a low on the DIR allows data transmissions from B to A.
9.2 Functional Block Diagram
Figure 10. Logic Diagram (Positive Logic)
9.3 Feature Description
9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V
Power-Supply Range
Both V
CCA
and V
CCB
can be supplied at any voltage between 1.65 V and 5.5 V, making the device suitable for
translating between any of the voltage nodes (1.8-V, 2.5-V, 3.3-V and 5-V).
9.3.2 Support High Speed Translation
SN74LVC1T45 can support high data rate applications. The translated signal data rate can be up to 420 Mbps
when the signal is translated from 3.3 V to 5 V.
9.3.3 I
off
Supports Partial Power-Down Mode Operation
I
off
will prevent backflow current by disabling I/O output circuits when device is in partial-power-down mode.
9.4 Device Functional Modes
Table 1. Function Table
(1)
INPUT
OPERATION
DIR
L B data to A bus
H A data to B bus
(1) Input circuits of the data I/Os always are active.
12 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVC1T45