Datasheet

1
2
3
6
5
4
A
Y
A
/B
V
CC
A
B
Figure 1. 2-to-1 Data Selector With Inverted
Output
1
2
3
6
5
4
B
Y
A
V
CC
A
Y
B
Figure 2. 2-Input NAND Gate
A
Y
B
1
2
3
6
5
4
B
Y
A
V
CC
A
Y
B
Figure 3. 2-Input NOR Gate With One Inverted
Input
2-Input AND Gate With One Inverted Input
1
2
3
6
5
4
B
Y
A
V
CC
Figure 4. 2-Input NAND Gate With One
Inverted Input
2-Input OR Gate With One Inverted Input
1
2
3
6
5
4
B
Y
A
V
CC
Figure 5. 2-Input NOR Gate
A/B
Y
B
A
Y
B
A
Y
B
GND
GND GND
A
Y
B
GND
1
2
3
6
5
4
Y
A
V
CC
Figure 6. Noninverted Buffer
YA
GND
GND
1
2
3
6
5
4
Y
V
CC
Figure 7. Inverter
YA
GND
A
SN74LVC1G98
www.ti.com SCES417K –DECEMBER 2002– REVISED OCTOBER 2011
LOGIC CONFIGURATIONS
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN74LVC1G98