Datasheet

3
1
6
In2
In1
In0
4
Y
SN74LVC1G98
SCES417K –DECEMBER 2002– REVISED OCTOBER 2011 www.ti.com
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
NanoFree™ – WCSP (DSBGA)
Reel of 3000 SN74LVC1G98YZPR _ _ _CW_
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000 SN74LVC1G98DBVR
SOT (SOT-23) – DBV C98_
Reel of 250 SN74LVC1G98DBVT
Reel of 3000 SN74LVC1G98DCKR
–40°C to 85°C
SOT (SC-70) – DCK CW_
Reel of 250 SN74LVC1G98DCKT
SOT (SOT-563) – DRL Reel of 4000 SN74LVC1G98DRLR CW_
QFN – DRY Reel of 5000 SN74LVC1G98DRYR CW
µQFN – DSF Reel of 5000 SN74LVC1G98DSFR CW
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
In2 In1 In0
L L L H
L L H H
L H L L
L H H L
H L L H
H L H L
H H L H
H H H L
LOGIC DIAGRAM (POSITIVE LOGIC)
FUNCTION SELECTION TABLE
LOGIC FUNCTION FIGURE NO.
2-to-1 data selector with inverted output 1
2-input NAND gate 2
2-input NOR gate with one inverted input 3
2-input AND gate with one inverted input 3
2-input NAND gate with one inverted input 4
2-input OR gate with one inverted input 4
2-input NOR gate 5
Noninverted buffer 6
Inverter 7
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Product Folder Link(s): SN74LVC1G98