Datasheet

LOGIC CONFIGURATIONS
1
2
3
6
5
4
A
Y
A/B
V
CC
Y
B
GND
A
B
A/B
1
2
3
6
5
4
B
Y
A
V
CC
Y
GND
A
B
1
2
3
6
5
4
B
Y
A
V
CC
A
Y
B
A
Y
B
GND
A
Y
B
A
Y
B
1
2
3
6
5
4
B
Y
A
V
CC
GND
1
2
3
6
5
4
B
Y
A
V
CC
A
Y
B
GND
1
2
3
6
5
4
Y
A
V
CC
YA
GND
1
2
3
6
5
4
Y
V
CC
YA
GND
A
SN74LVC1G97-Q1
www.ti.com ........................................................................................................................................................ SCES561D – MARCH 2004 – REVISED APRIL 2008
Figure 1. 2-to-1 Data Selector Figure 2. 2-Input AND Gate
Figure 3. 2-Input OR Gate With One Inverted Input Figure 4. 2-Input AND Gate With One Inverted Input
2-Input NAND Gate With One Inverted Input 2-Input NOR Gate With One Inverted Input
Figure 5. 2-Input OR Gate Figure 6. Inverter
Figure 7. Noninverted Buffer
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