Datasheet

TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
7
2
6
5
3
1
SN74LVC1G74
SCES794C –SEPTEMBER 2009–REVISED NOVEMBER 2012 www.ti.com
ORDERING INFORMATION
ORDERABLE TOP-SIDE
T
A
PACKAGE
(1) (2)
PART NUMBER MARKING
(3)
NanoFree™ – WCSP (DSBGA)
Reel of 3000 SN74LVC1G74YZPR _ _ _DP_
0.23-mm Large Bump – YZP (Pb-free)
SN74LVC1G74RSER
–40°C to 85°C
QFN - RSE
Reel of 3000 SN74LVC1G74RSE2
(4)
DP
µQFN - DQE SN74LVC1G74DQER
SSOP – DCT Reel of 3000 SN74LVC1G74DCTR N74_ _ _
SN74LVC1G74DCUR
–40°C to 125°C Reel of 3000
VSSOP – DCU SN74LVC1G74DCURG4 N74_
Reel of 250 SN74LVC1G74DCUT
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
(4) Pin 1 orientation at quadrant 3 in Tape.
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H
(1)
H
(1)
H H ↑ H H L
H H ↑ L L H
H H L X Q
0
Q
0
(1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
LOGIC DIAGRAM (POSITIVE LOGIC)
2 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G74