Datasheet

1
2
3
6
5
4
A
Y
B
V
CC
Y
A
B
A
Y
B
1
2
3
6
5
4
A
Y
B
V
CC
A
Y
B
A
Y
B
1
2
3
6
5
4
A
Y
B
V
CC
A
Y
B
A
Y
B
1
2
3
6
5
4
A
Y
B
V
CC
A
Y
B
A
Y
B
1
2
3
6
5
4
A
Y
B
V
CC
A
Y
B
SN74LVC1G58
www.ti.com SCES415M –NOVEMBER 2002–REVISED APRIL 2013
LOGIC CONFIGURATIONS
Figure 2. 2-Input NAND Gate Figure 3. 2-Input AND Gate With Inverted A Input
Figure 4. 2-Input AND Gate With Inverted B Input Figure 5. 2-Input OR Gate
Figure 6. 2-Input XOR Gate
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