Datasheet
A
2
4
Y
A
1
3
Y
SN74LVC1G34
SCES519I –DECEMBER 2003– REVISED JUNE 2011
www.ti.com
DESCRIPTION/ORDERING INFORMATION
This single buffer gate is designed for 1.65-V to 5.5-V V
CC
operation. The SN74LVC1G34 performs the Boolean
function Y = A in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Table 3. ORDERING INFORMATION
TOP-SIDE
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
MARKING
(2)
NanoFree™ – WCSP (DSBGA)
SN74LVC1G34YFPR _ _ _ C9_
0.23-mm Large Bump – YFP
Reel of 3000
NanoFree™ – WCSP (DSBGA)
SN74LVC1G34YZPR _ _ _ C9_
0.23-mm Large Bump – YZP
NanoFree™ – WCSP (DSBGA) _ _ _ _
Reel of 3000 SN74LVC1G34YZVR
0.23-mm Large Bump – YZV (Pb-free) C9
µQFN – DSF Reel of 5000 SN74LVC1G34DSFR C9
–40°C to 85°C
QFN – DRY Reel of 5000 SN74LVC1G34DRYR C9
Reel of 3000 SN74LVC1G34DBVR
SOT (SOT-23) –DBV C34_
Reel of 250 SN74LVC1G34DBVT
Reel of 3000 SN74LVC1G34DCKR
SOT (SC-70) – DCK
Reel of 250 SN74LVC1G34DCKT C9_
SOT (SOT-553) – DRL Reel of 4000 SN74LVC1G34DRLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
YZV: The actual top-side marking is on two lines. Line 1 has four characters to denote year, month, day, and assembly/test site. Line 2
has two characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUT OUTPUT
A Y
H H
L L
LOGIC DIAGRAM (POSITIVE LOGIC)
(DBV, DCK, DSF, DRY, DRL, and YZP Package)
LOGIC DIAGRAM (POSITIVE LOGIC)
(YFP and YZV Package)
2 Copyright © 2003–2011, Texas Instruments Incorporated