Datasheet
SN74LVC1G3157
SCES424H –JANUARY 2003–REVISED MAY 2012
www.ti.com
Recommended Operating Conditions
(1)
MIN MAX UNIT
V
CC
Supply voltage 1.65 5.5 V
V
I/O
Switch input/output voltage 0 V
CC
V
V
IN
Control input voltage 0 5.5 V
V
CC
= 1.65 V to 1.95 V V
CC
× 0.75
V
IH
High-level input voltage, control input V
V
CC
= 2.3 V to 5.5 V V
CC
× 0.7
V
CC
= 1.65 V to 1.95 V V
CC
× 0.25
V
IL
Low-level input voltage, control input V
V
CC
= 2.3 V to 5.5 V V
CC
× 0.3
V
CC
= 1.65 V to 1.95 V 20
V
CC
= 2.3 V to 2.7 V 20
Δt/Δv Input transition rise or fall rate ns/V
V
CC
= 3 V to 3.6 V 10
V
C C
= 4.5 V to 5.5 V 10
T
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
I
= 0 V I
O
= 4 mA 11 20
1.65 V
V
I
= 1.65 V I
O
= –4 mA 15 50
V
I
= 0 V I
O
= 8 mA 8 12
2.3 V
V
I
= 2.3 V I
O
= –8 mA 11 30
See Figure 1
r
on
On-state switch resistance
(2)
V
I
= 0 V I
O
= 24 mA 7 9 Ω
and Figure 2
3 V
V
I
= 3 V I
O
= –24 mA 9 20
V
I
= 0 V I
O
= 30 mA 6 7
V
I
= 2.4 V I
O
= –30 mA 4.5 V 7 12
V
I
= 4.5 V I
O
= –30 mA 7 15
I
A
= –4 mA 1.65 V 140
I
A
= –8 mA 2.3 V 45
On-state switch resistance 0 ≤ V
Bn
≤ V
CC
r
range
Ω
over signal range
(2) (3)
(see Figure 1 and Figure 2)
I
A
= –24 mA 3 V 18
I
A
= –30 mA 4.5 V 10
V
Bn
= 1.15 V I
A
= –4 mA 1.65 V 0.5
Difference of on-state
V
Bn
= 1.6 V I
A
= –8 mA 2.3 V 0.1
Δr
on
resistance between See Figure 1 Ω
V
Bn
= 2.1 V I
A
= –24 mA 3 V 0.1
switches
(2) (4) (5)
V
Bn
= 3.15 V I
A
= –30 mA 4.5 V 0.1
I
A
= –4 mA 1.65 V 110
I
A
= –8 mA 2.3 V 26
r
on(flat)
ON resistance flatness
(2) (4) (6)
0 ≤ V
Bn
≤ V
CC
Ω
I
A
= –24 mA 3 V 9
I
A
= –30 mA 4.5 V 4
±1
Off-state switch leakage 1.65 V to
I
off
(7)
0 ≤ V
I
, V
O
≤ V
CC
(see Figure 3 ) μA
current 5.5 V
±0.05 ±1
(1)
(1) T
A
= 25°C
(2) Measured by the voltage drop between I/O pins at the indicated current through the switch. On-state resistance is determined by the
lower of the voltages on the two (A or B) ports.
(3) Specified by design
(4) Δr
on
= r
on(max)
– r
on(min)
measured at identical V
CC
, temperature, and voltage levels
(5) This parameter is characterized, but not production tested.
(6) Flatness is defined as the difference between the maximum and minimum values of on-state resistance over the specified range of
conditions.
(7) I
off
is the same as I
S(off)
(off-state switch leakage current).
4 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G3157