Datasheet

A Y
2 4
A Y
1 3
SN74LVC1G14
SCES647A SEPTEMBER 2005 REVISED JUNE 2011
www.ti.com
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
NanoFree WCSP (DSBGA)
Reel of 3000 SN74LVC1G14YZPR _ _ _CF_
0.23-mm Large Bump YZP (Pb-free)
NanoFree WCSP (DSBGA) _ _ _ _
Reel of 3000 SN74LVC1G14YZVR
0.23-mm Large Bump YZV (Pb-free) CF
Reel of 3000 SN74LVC1G14DBVR
SOT (SOT-23) DBV C14_
Reel of 250 SN74LVC1G14DBVT
40°C to 85°C
Reel of 3000 SN74LVC1G14DCKR
SOT (SC-70) DCK CF_
Reel of 250 SN74LVC1G14DCKT
SOT (SOT-553) DRL Reel of 4000 SN74LVC1G14DRLR CF_
µQFN DSF Reel of 5000 SN74LVC1G14DSFR CF
QFN DRY Reel of 5000 SN74LVC1G14DRYR CF
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
YZV: The actual top-side marking is on two lines. Line 1 has four characters to denote year, month, day, and assembly/test site. Line 2
has two characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUT OUTPUT
A Y
H L
L H
LOGIC DIAGRAM (POSITIVE LOGIC)
(DBV, DCK, DRL, DSF, DRY, and YZP Package)
LOGIC DIAGRAM (POSITIVE LOGIC)
(YZV Package)
2 Copyright © 20052011, Texas Instruments Incorporated