Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74LVC SOT 23 5

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FEATURES

Seemechanicaldrawingsfordimensions.

DBVPACKAGE

(TOP VIEW)

GND Y

DCKPACKAGE

(TOP VIEW)

GND

YEP OR YZP PACKAGE

(BOTTOMVIEW)

GND

DESCRIPTION/ORDERING INFORMATION

SN74LVC1G132

SINGLE 2-INPUT NAND GATE

WITH SCHMITT-TRIGGER INPUTS

SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006

• I

off

Supports Partial-Power-Down Mode

Operation

• Available in Texas Instruments NanoStar™

and NanoFree™ Packages • Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• Supports 5-V V

Operation

• ESD Protection Exceeds JESD 22

• Inputs Accept Voltages to 5.5 V

– 2000-V Human-Body Model (A114-A)

• Max t

of 5.3 ns at 3.3 V

– 200-V Machine Model (A115-A)

• Low Power Consumption, 10- µ A Max I

– 1000-V Charged-Device Model (C101)

• ± 24-mA Output Drive at 3.3 V

The SN74LVC1G132 contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V

operation and performs the Boolean function Y = A • B or Y = A + B in positive logic.

Because of Schmitt action, this device has different input threshold levels for positive-going (V

T+

) and

negative-going (V

T–

) signals.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

NanoStar™ – WCSP (DSBGA)

SN74LVC1G132YEPR

0.23-mm Large Bump – YEP

Reel of 3000 _ _ _D5_

NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP SN74LVC1G132YZPR

(Pb-free)

–40°C to 85°C

Reel of 3000 SN74LVC1G132DBVR

SOT (SOT-23) – DBV C3B_

Reel of 250 SN74LVC1G132DBVT

Reel of 3000 SN74LVC1G132DCKR

SOT (SC-70) – DCK D5_

Reel of 250 SN74LVC1G132DCKT

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar, NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 • FEATURES • • • • • • Available in Texas Instruments NanoStar™ and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5.3 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.
PAGE 2
SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 FUNCTION TABLE INPUTS B OUTPUT Y L L H L H H H L H H H L A LOGIC DIAGRAM (POSITIVE LOGIC) A Y B Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 6.5 V range (2) VI Input voltage –0.5 6.
PAGE 3
SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 Recommended Operating Conditions VCC Supply voltage VI Input voltage VO Output voltage IOH (1) Operating Data retention only High-level output current MIN MAX 1.65 5.5 1.5 5.5 V 0 VCC V VCC = 1.65 V –4 VCC = 2.3 V –8 –16 VCC = 3 V –32 4 VCC = 2.3 V 8 16 VCC = 3 V (1) Operating free-air temperature mA 24 VCC = 4.5 V TA mA –24 VCC = 1.
PAGE 4
SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP (1) MAX 1.65 V 0.79 1.16 2.3 V 1.11 1.56 TEST CONDITIONS VCC VT+ Positive-going input threshold voltage 3V 1.5 1.87 4.5 V 2.16 2.74 5.5 V 2.61 3.33 1.65 V 0.39 0.62 2.3 V 0.58 0.87 3V 0.84 1.14 4.5 V 1.41 1.79 5.5 V 1.87 2.
PAGE 5
SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ±0.15 V VCC = 2.5 V ±0.2 V VCC = 3.3 V ±0.3 V VCC = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 4 16 3 7.
PAGE 6
SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
PAGE 7
SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74LVC1G132DBVR SOT-23 3000 180.0 8.4 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G132DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G132DCKR SC70 DCK 5 3000 180.0 8.4 2.25 2.4 1.22 4.0 8.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G132DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74LVC1G132DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 SN74LVC1G132DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74LVC1G132DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G132DCKT SC70 DCK 5 250 202.0 201.0 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.