Datasheet
YA
SN54LVC14A, SN74LVC14A
SCAS285Z –MARCH 1993–REVISED JANUARY 2014
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
(Each Inverter)
INPUT OUTPUT
A Y
H L
L H
Logic Diagram, Each Inverter (Positive Logic)
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 V
V
I
Input voltage range
(2)
–0.5 6.5 V
V
O
Output voltage range
(2)
\
(3)
–0.5 V
CC
+ 0.5 V
I
IK
Input clamp current V
I
< 0 –50 mA
I
OK
Output clamp current V
O
< 0 –50 mA
I
O
Continuous output current ±50 mA
Continuous current through V
CC
or GND ±100 mA
D package
(4)
86
DB package
(4)
96
DGV package
(4)
127
θ
JA
Package thermal impedance °C/W
NS package
(4)
76
PW package
(4)
113
RGY package
(5)
47
T
stg
Storage temperature range –65 150 °C
P
tot
Power dissipation T
A
= –40°C to 125°C
(6)(7)
500 mW
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V
CC
is provided in the Recommended Operating Conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
(6) For the D package: above 70°C, the value of P
tot
derates linearly with 8 mW/K.
(7) For the DB, DGV, NS, and PW packages: above 60°C, the value of P
tot
derates linearly with 5.5 mW/K.
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