Datasheet

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APPLICATION INFORMATION
CTRL
(1)
R
s
≅ 1 kΩ
C
L
≅ 16 pF
C
2
≅ 32 pF
XOUT
XIN
OSCOUT
Y
A
Optional Signal-Conditioning Stage
C
LOAD
R
LOAD
C
LOAD
R
F
≅ 2.2 MΩ
C
1
≅ 32 pF
GND
1
2
3
4
5
6
7
8
V
CC
R
LOAD
(1) CTRL should be tied to logic high during normal operation of the oscillator circuit. To disable the oscillator circuit, connect CTRL to logic low.
B) Oscillator Circuit in DCT or DCU Pinout
Practical Design Tips
SN74LVC1404
OSCILLATOR DRIVER
FOR CRYSTAL OSCILLATOR OR CERAMIC RESONATOR
SCES469D – AUGUST 2003 – REVISED JANUARY 2007
• The open-loop gain of the unbuffered inverter decreases as power-supply voltage decreases. This decreases
the closed-loop gain of the oscillator circuit. The value of R
s
can be decreased to increase the closed-loop
gain, while maintaining the power dissipation of the crystal within the maximum limit.
• R
s
and C
2
form a low-pass filter and reduce spurious oscillations. Component values can be adjusted, based
on the desired cutoff frequency.
• C
2
can be increased over C
1
to increase the phase shift and help in start-up of the oscillator. Increasing C
2
may affect the duty cycle of the output voltage.
• At high frequency, phase shift due to R
s
becomes significant. In this case, R
s
can be replaced by a capacitor
to reduce the phase shift.
9
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