Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74LVC SOIC 14

www.ti.com

FEATURES

D, DB, NS, OR PW PACKAGE

(TOP VIEW)

GND

RGY PACKAGE

(TOP VIEW)

1 14

7 8

GND

DESCRIPTION/ORDERING INFORMATION

SN74LVC10A

TRIPLE 3-INPUT POSITIVE-NAND GATE

SCAS284O – JANUARY 1993 – REVISED JULY 2005

• Operates From 1.65 V to 3.6 V

• Specified From –40 ° C to 85 ° C and

– 40 ° C to 125 ° C

• Inputs Accept Voltages to 5.5 V

• Max t

of 4.9 ns at 3.3 V

• Typical V

OLP

(Output Ground Bounce)

< 0.8 V at V

= 3.3 V, T

= 25 ° C

• Typical V

OHV

(Output V

Undershoot)

> 2 V at V

= 3.3 V, T

= 25 ° C

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V V

operation.

The SN74LVC10A performs the Boolean function Y = A • B • C or Y = A + B + C in positive logic.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

–40 ° C to 85 ° C QFN – RGY Reel of 1000 SN74LVC10ARGYR LC10A

Tube of 50 SN74LVC10AD

SOIC – D Reel of 2500 SN74LVC10ADR LVC10A

Reel of 250 SN74LVC10ADT

SOP – NS Reel of 2000 SN74LVC10ANSR LVC10A

–40 ° C to 125 ° C

SSOP – DB Reel of 2000 SN74LVC10ADBR LC10A

Tube of 90 SN74LVC10APW

TSSOP – PW Reel of 2000 SN74LVC10APWR LC10A

Reel of 250 SN74LVC10APWT

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y RGY PACKAGE (TOP VIEW) 1B 2A 2B 2C 2Y VCC • 1 1 14 13 1C 12 1Y 2 3 4 11 3C 5 6 10 3B 9 3A 7 8 3Y • 1A 1B 2A 2B 2C 2Y GND 1A • • • D, DB, NS, OR PW PACKAGE (TOP VIEW) Operates From 1.65 V to 3.6 V Specified From –40°C to 85°C and – 40°C to 125°C Inputs Accept Voltages to 5.5 V Max tpd of 4.9 ns at 3.
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 FUNCTION TABLE (EACH GATE) INPUTS A B C OUTPUT Y H H H L L X X H X L X H X X L H LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC) A Y B C Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Output voltage range (2) (3) –0.5 VCC + 0.
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 Recommended Operating Conditions (1) TA = 25°C VCC Supply voltage VIH High-level input voltage Low-level input voltage VIL VI Input voltage VO Output voltage High-level output current IOH Operating Data retention only MAX MIN MAX MIN MAX 1.65 3.6 1.65 3.6 1.65 3.6 1.5 1.5 1.5 0.65 × VCC 0.65 × VCC 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 VCC = 2.7 V to 3.
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) A, B, or C TO (OUTPUT) Y VCC TA = 25°C –40 TO 85°C TYP MAX MIN MAX MIN MAX 1.8 V ± 0.15 V 1 4.2 10.1 1 10.6 1 12.1 2.5 V ± 0.2 V 1 2.9 7.3 1 7.8 1 9.9 2.7 V 1 3.1 5.6 1 5.8 1 7.4 3.3 V ± 0.3 V 1 2.7 4.7 1 4.9 1 6 3.
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCAS284O – JANUARY 1993 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC10ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LVC10ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC10ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC10ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LVC10ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LVC10ADT SOIC D 14 250 367.0 367.0 38.0 SN74LVC10ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LVC10APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC10APWT TSSOP PW 14 250 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.