Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74LV SOIC 14

 

   

SCLS392F − APRIL 1998 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 8 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The ’LV86A devices are quadruple 2-input

exclusive-OR gates designed for 2-V to 5.5-V V

operation.

These devices contain four independent 2-input

exclusive-OR gates. They perform the Boolean

function

Y = A ę B or Y = A

B + AB in positive logic.

A common application is as a true/complement

element. If one of the inputs is low, the other input

is reproduced in true form at the output. If one of

the inputs is high, the signal on the other input is

reproduced inverted at the output.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − D

Tube of 50 SN74LV86AD

LV86A

SOIC − D

Reel of 2500 SN74LV86ADR

LV86A

SOP − NS Reel of 2000 SN74LV86ANSR 74LV86A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV86ADBR LV86A

−40°C to 85°C

Tube of 90 SN74LV86APW

TSSOP − PW

Reel of 2000 SN74LV86APWR

LV86A

TSSOP − PW

Reel of 250 SN74LV86APWT

LV86A

TVSOP − DGV Reel of 2000 SN74LV86ADGVR LV86A

CDIP − J Tube of 25 SNJ54LV86AJ SNJ54LV86AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV86AW SNJ54LV86AW

−55 C to 125 C

LCCC - FK Tube of 55 SNJ54LV86AFK SNJ54LV86AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

GND

SN54LV86A ...J OR W PACKAGE

SN74LV86A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54LV86A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

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+(*(%&&*.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (19 pages)

PAGE 1
SCLS392F − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.
PAGE 2
SCLS392F − APRIL 1998 − REVISED APRIL 2005 FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y L L L L H H H L H H H L exclusive-OR logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. Exclusive OR =1 These are five equivalent exclusive-OR symbols valid for an ’LV86A gate in positive logic; negation can be shown at any two ports.
PAGE 3
SCLS392F − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV86A VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V High-level output current Low-level output current Input transition rise or fall rate MIN MAX 2 5.5 1.5 MIN MAX 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.
PAGE 4
SCLS392F − APRIL 1998 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV86A PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA VCC MIN 2 V to 5.5 V IOH = −6 mA IOH = −12 mA IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA II ICC VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 SN74LV86A TYP MAX MIN 2.3 V VCC−0.
PAGE 5
SCLS392F − APRIL 1998 − REVISED APRIL 2005 noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV86A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.2 0.8 V Quiet output, minimum dynamic VOL −0.1 −0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3.1 High-level dynamic input voltage V 2.
PAGE 6
SCLS392F − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% V
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV86ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV86ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV86ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV86ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LV86ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LV86ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LV86ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LV86APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV86APWT TSSOP PW 14 250 367.0 367.0 35.
PAGE 12
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 13
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 19
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