Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74LV Positive slope 25 MHz TSSOP 20

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SCLS589 − AUGUST 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Can Be Used as Two 16-Bit Counters or a

Single 32-Bit Counter

D 2-V to 5.5-V V

Operation

D Max t

of 25 ns at 5 V (RCLK to Y)

D Typical V

OLP

(Output Ground Bounce)

<0.7 V at V

= 5 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>4.4 V at V

= 5 V, T

= 25°C

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The SN74LV8154 is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V V

operation.

This 16-bit counter (A or B) feeds a 16-bit storage register, and each storage register is further divided into an

upper byte and lower byte. The GAL

, GAU, GBL, GBU inputs are used to select the byte that needs to be output

at Y0−Y7. CLKA is the clock for A counter, and CLKB is the clock for B counter. RCLK is the clock for the A and

B storage registers. All three clock signals are positive-edge triggered.

A 32-bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA

to CLKBEN.

To ensure the high-impedance state during power up or power down, GAL

, GAU, GBL, and GBU should be tied

to V

through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability

of the driver.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74LV8154N SN74LV8154N

−40°C to 85°C

TSSOP − PW

Tube SN74LV8154PW

LV8154

−40 C to 85 C

TSSOP − PW

Tape and reel SN74LV8154PWR

LV8154

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

N OR PW PACKAGE

(TOP VIEW)

CLKA

CLKB

GAL

GAU

GBL

GBU

RCLK

RCOA

CLKBEN

GND

CCLR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (14 pages)

PAGE 1
SCLS589 − AUGUST 2004 D Can Be Used as Two 16-Bit Counters or a D D D D D D D N OR PW PACKAGE (TOP VIEW) Single 32-Bit Counter 2-V to 5.5-V VCC Operation Max tpd of 25 ns at 5 V (RCLK to Y) Typical VOLP (Output Ground Bounce) <0.7 V at VCC = 5 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >4.
PAGE 2
SCLS589 − AUGUST 2004 FUNCTION TABLE (each buffer) INPUTS GAL GAU GBL GBU OUTPUT Yn Lower byte in A register L H H H H L H H Upper byte in A register H H L H Lower byte in B register H H H L Upper byte in B register H H H H Z Combinations of GAL, GAU, GBL, GBU, other than those shown above, are prohibited. If more than one input is L at the same time, the output data (Y0−Y7) may be invalid.
PAGE 3
SCLS589 − AUGUST 2004 block diagram R R R R R R CCKB CCKBEN R R R R R R R R R 16-Bit Counter B R R R R R R R R R R R R R R R 4 to 1 Dec Y0 4 to 1 Dec Y1 4 to 1 Dec Y2 4 to 1 Dec Y3 4 to 1 Dec Y4 4 to 1 Dec Y5 4 to 1 Dec Y6 4 to 1 Dec Y7 R R RCLK CCKA CCLR 16-Bit Counter A GAL GAU GBL RCOA GBU absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Sup
PAGE 4
SCLS589 − AUGUST 2004 recommended operating conditions (see Note 4) VCC VCC Supply voltage 2V VIH 3 V to 3.6 V High-level input voltage 4.5 V to 5.5 V MIN MAX 2 5.5 VCC × 0.7 VCC × 0.7 0.5 4.5 V to 5.5 V VI Input voltage VO Output voltage 5.5 V High or low state 0 3-state 0 VCC 5.5 V −50 µA Yn outputs Yn outputs −6 −12 2V −50 3 V to 3.6 V −6 4.5 V to 5.5 V −12 2V 50 3 V to 3.6 V 6 4.5 V to 5.
PAGE 5
SCLS589 − AUGUST 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Yn VOH RCOA Yn VOL RCOA MIN IOH = −50 µA IOH = −6 mA 2V 3V 2.48 IOH = −12 mA IOH = −50 µA 4.5 V 3.8 2V 1.9 IOH = −6 mA IOH = −12 mA 3V 2.48 4.5 V 3.8 TYP MAX V 2V 0.1 3V 0.44 IOL = 12 mA IOL = 50 µA 4.5 V 0.55 2V 0.1 IOL = 6 mA IOL = 12 mA 3V 0.44 4.5 V 0.
PAGE 6
SCLS589 − AUGUST 2004 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.
PAGE 7
SCLS589 − AUGUST 2004 switching characteristics over recommended operating VCC = 5 V ± 0.
PAGE 8
SCLS589 − AUGUST 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Jan-2013 Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.