Datasheet

SN54LV74A, SN74LV74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS381L − AUGUST 1997 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the

other inputs. When PRE

and CLR are inactive (high), data at the data (D) inputs meeting the setup-time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

These devices are fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the

outputs, preventing damaging current backflow through the devices when they are powered down.

FUNCTION TABLE

INPUTS OUTPUTS

PRE CLR CLK D Q Q

L H X X H L

H LXXLH

L LXXH

†

H H ↑ HHL

H H ↑ LLH

H H L X Q

†

This configuration is nonstable; that is, it does not

persist when PRE

or CLR returns to its inactive

(high) level.

logic diagram, each flip-flop (positive logic)

PRE

CLK

CLR