Datasheet

SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O − APRIL 1998 − REVISED JANUARY 2011
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C SN54LV595A SN74LV595A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
SRCLK high or low 5.5 5.5 5.5
t
w
Pulse duration
RCLK high or low
5.5 5.5 5.5
ns
t
w
Pulse duration
SRCLR low 5 5 5
ns
SER before SRCLK↑ 3.5 3.5 3.5
t
Setup time
SRCLK↑ before RCLK↑
†
8 8.5 8.5
ns
t
su
Setup time
SRCLR
low before RCLK↑ 8 9 9
ns
SRCLR high (inactive) before SRCLK↑ 3 3 3
t
h
Hold time SER after SRCLK↑ 1.5 1.5 1.5 ns
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C SN54LV595A SN74LV595A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
SRCLK high or low 5 5 5
t
w
Pulse duration
RCLK high or low
5 5 5
ns
t
w
Pulse duration
SRCLR low 5.2 5.2 5.2
ns
SER before SRCLK↑ 3 3 3
t
Setup time
SRCLK↑ before RCLK↑
†
5 5 5
ns
t
su
Setup time
SRCLR
low before RCLK↑ 5 5 5
ns
SRCLR high (inactive) before SRCLK↑ 2.5 2.5 2.5
t
h
Hold time SER after SRCLK↑ 2 2 2 ns
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
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