Datasheet

 
  
  
SCLS413I − APRIL 1998 − REVISED APRIL 2005
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C SN54LV594A SN74LV594A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
t
w
Pulse duration
RCLK or SRCLK high or low 7 7.5 7.5
ns
t
w
Pulse duration
RCLR
or SRCLR low 6 6.5 6.5
ns
SER before SRCLK↑ 5.5 5.5 5.5
SRCLK↑ before RCLK↑
†
8 9 9
t
su
Setup time
SRCLR
low before RCLK↑ 8.5 9.5 9.5
ns
t
su
Setup time
SRCLR high (inactive) before SRCLK↑ 6 6.8 6.8
ns
RCLR high (inactive) before RCLK↑ 6.7 7.6 7.6
t
h
Hold time SER after SRCLK↑ 1.5 1.5 1.5 ns
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C SN54LV594A SN74LV594A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
t
w
Pulse duration
RCLK or SRCLK high or low 5.5 5.5 5.5
ns
t
w
Pulse duration
RCLR
or SRCLR low 5 5 5
ns
SER before SRCLK↑ 3.5 3.5 3.5
SRCLK↑ before RCLK↑
†
8 8.5 8.5
t
su
Setup time
SRCLR
low before RCLK↑ 8 9 9
ns
t
su
Setup time
SRCLR high (inactive) before SRCLK↑ 4.2 4.8 4.8
ns
RCLR high (inactive) before RCLK↑ 4.6 5.3 5.3
t
h
Hold time SER after SRCLK↑ 1.5 1.5 1.5 ns
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C SN54LV594A SN74LV594A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
t
w
Pulse duration
RCLK or SRCLK high or low 5 5 5
ns
t
w
Pulse duration
RCLR
or SRCLR low 5.2 5.2 5.2
ns
SER before SRCLK↑ 3 3 3
SRCLK↑ before RCLK↑
†
5 5 5
t
su
Setup time
SRCLR
low before RCLK↑ 5 5 5
ns
t
su
Setup time
SRCLR high (inactive) before SRCLK↑ 2.9 3.3 3.3
ns
RCLR high (inactive) before RCLK↑ 3.2 3.7 3.7
t
h
Hold time SER after SRCLK↑ 2 2 2 ns
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
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