Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver TSSOP 20

OE1

GND

OE2

DB, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

RGY PACKAGE

(TOP VIEW)

1 20

10 11

OE2

OE1

GND

SN74LV541AT

www.ti.com

SCES573B –JUNE 2004–REVISED JULY 2013

OCTAL BUFFER/DRIVER

WITH 3-STATE OUTPUTS

Check for Samples: SN74LV541AT

FEATURES

DESCRIPTION

The SN74LV541AT is designed for 4.5-V to 5.5-V

• Inputs Are TTL-Voltage Compatible

operation. The inputs are TTL-voltage

• 4.5-V to 5.5-V V

Operation

compatible, which allows them to be interfaced with

• Typical t

of 4 ns at 5 V

bipolar outputs and 3.3-V devices. The device also

can be used to translate from 3.3 V to 5 V.

• Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 5 V, T

= 25°C

This device is ideal for driving bus lines or buffer

memory address registers. It features inputs and

• Typical V

OHV

(Output V

Undershoot)

outputs on opposite sides of the package to facilitate

>2.3 V at V

= 5 V, T

= 25°C

printed circuit board layout.

• Supports Mixed-Mode Voltage Operation on

All Ports

The 3-state control gate is a two-input AND gate with

active-low inputs so that, if either output-enable (OE1

• I

off

Supports Partial-Power-Down Mode

or OE2) input is high, all corresponding outputs are in

Operation

the high-impedance state. The outputs provide

• Latch-Up Performance Exceeds 250 mA Per

noninverted data when they are not in the high-

JESD 17

impedance state.

• ESD Protection Exceeds JESD 22

To ensure the high-impedance state during power up

– 2000-V Human-Body Model (A114-A)

or power down, OE shall be tied to VCC through a

pullup resistor; the minimum value of the resistor is

– 200-V Machine Model (A115-A)

determined by the current-sinking capability of the

– 1000-V Charged-Device Model (C101)

driver.

This device is fully specified for partial-power-down

applications using I

off

. The I

off

circuitry disables the

outputs, preventing damaging current backflow

through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

PAGE 1
SN74LV541AT www.ti.com SCES573B – JUNE 2004 – REVISED JULY 2013 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS Check for Samples: SN74LV541AT FEATURES DESCRIPTION • • • • The SN74LV541AT is designed for 4.5-V to 5.5-V VCC operation. The inputs are TTL-voltage compatible, which allows them to be interfaced with bipolar outputs and 3.3-V devices. The device also can be used to translate from 3.3 V to 5 V. 1 • • • • • Inputs Are TTL-Voltage Compatible 4.5-V to 5.
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SN74LV541AT SCES573B – JUNE 2004 – REVISED JULY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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SN74LV541AT www.ti.com SCES573B – JUNE 2004 – REVISED JULY 2013 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 V VO Output voltage range applied in the high or low state (2) (3) –0.5 VCC + 0.
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SN74LV541AT SCES573B – JUNE 2004 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMET ER TEST CONDITIONS VOH VOL TA = –40°C to 85°C SN74LV541AT SN74LV541AT MIN TYP IOH = –50 μA 4.5 V 4.4 4.5 IOH = –16 mA 4.5 V 3.8 IOL = 50 μA 4.5 V IOL = 16 mA 4.5 V MAX 0 MIN TA = –40°C to 125°C Recommended UNIT SN74LV541AT MAX MIN 4.4 4.4 3.8 3.8 TYP MAX V 0.1 0.1 0.1 0.55 0.
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SN74LV541AT www.ti.com SCES573B – JUNE 2004 – REVISED JULY 2013 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND S1 Open VCC GND VCC tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.
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SN74LV541AT SCES573B – JUNE 2004 – REVISED JULY 2013 www.ti.com REVISION HISTORY Changes from Revision A (August 2005) to Revision B • 6 Page Added parameter values for –40 to 125°C temperature ratings. ..........................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 29-Jul-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74LV541ATDBR SSOP DB 20 2000 330.0 16.4 SN74LV541ATDGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV541ATDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV541ATDBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LV541ATDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LV541ATDWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LV541ATNSR SO NS 20 2000 367.0 367.0 45.0 SN74LV541ATPWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LV541ATPWT TSSOP PW 20 250 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.