Datasheet

SN54LV540A, SN74LV540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS409H − APRIL 1998 − REVISED APRIL 2005
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These devices are ideal for driving bus lines or buffer memory address registers. They feature inputs and
outputs on opposite sides of the package to facilitate printed circuit board layout.
The 3-state control gate is a two-input AND gate with active-low inputs so that, if either output
enable (OE1
or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs
provide inverted data when they are not in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OUTPUT
OE1 OE2 A
OUTPUT
Y
L L L H
L LH L
H XX Z
X H X Z
logic diagram (positive logic)
OE1
OE2
To Seven Other Channels
A1
Y1
1
19
2
18