Datasheet
SN74LV4052A-Q1
www.ti.com
SCLS469E –MARCH 2003–REVISED NOVEMBER 2012
RECOMMENDED OPERATING CONDITIONS
(1)
MIN MAX UNIT
V
CC
Supply voltage 2
(2)
5.5 V
V
CC
= 2 V 1.5
V
CC
= 2.3 V to 2.7 V V
CC
× 0.7
High-level input voltage,
V
IH
V
control inputs
V
CC
= 3 V to 3.6 V V
CC
× 0.7
V
CC
= 4.5 V to 5.5 V V
CC
× 0.7
V
CC
= 2 V 0.5
V
CC
= 2.3 V to 2.7 V V
CC
× 0.3
Low-level input voltage,
V
IL
V
control inputs
V
CC
= 3 V to 3.6 V V
CC
× 0.3
V
CC
= 4.5 V to 5.5 V V
CC
× 0.3
V
I
Control input voltage 0 5.5 V
V
IO
Input/output voltage 0 V
CC
V
V
CC
= 2.3 V to 2.7 V 200
Δt/Δv Input transition rise or fall rate V
CC
= 3 V to 3.6 V 100 ns/V
V
CC
= 4.5 V to 5.5 V 20
T
A
Operating free-air temperature SN74LV4052ATDRQ1, SN74LV4052ATPWRQ1 –40 105
°C
T
A
Operating free-air temperature SN74LV4052AQPWRQ1 –40 125
(1) Hold all unused inputs of the device at V
CC
or GND to ensure proper device operation. See the TI application report, Implications of
Slow or Floating CMOS Inputs, literature number SCBA004.
(2) With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. TI recommends transmitting only
digital signals at these low supply voltages.
THERMAL INFORMATION
SN74LV4052A-Q1
THERMAL METRIC
(1)
D PW UNIT
16 PINS 16 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
85.9 113.3 °C/W
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
44.6 48.1 °C/W
θ
JB
Junction-to-board thermal resistance
(4)
43.4 58.4 °C/W
ψ
JT
Junction-to-top characterization parameter
(5)
13.4 6.2 °C/W
ψ
JB
Junction-to-board characterization parameter
(6)
43.1 57.8 °C/W
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
— — °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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