Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 20

 

 

  

SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 6.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

These octal buffers/drivers are designed for 2-V to

5.5-V V

operation.

The ’LV240A devices are designed specifically to

improve both the performance and density of

3-state memory address drivers, clock drivers,

and bus-oriented receivers and transmitters.

These devices are organized as two 4-bit

buffers/line drivers with separate output-enable

(OE

) inputs. When OE is low, the device passes

data from the A inputs to the Y outputs. When OE

is high, the outputs are in the high-impedance

state.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − DW

Tube of 25 SN74LV240ADW

LV240A

SOIC − DW

Reel of 2000 SN74LV240ADWR

LV240A

SOP − NS Reel of 2000 SN74LV240ANSR 74LV240A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV240ADBR LV240A

−40°C to 85°C

Tube of 70 SN74LV240APW

TSSOP − PW

Reel of 2000 SN74LV240APWR

LV240A

TSSOP − PW

Reel of 250 SN74LV240APWT

LV240A

TVSOP − DGV Reel of 2000 SN74LV240ADGVR LV240A

CDIP − J Tube of 20 SNJ54LV240AJ SNJ54LV240AJ

−55°C to 125°C

CFP − W Tube of 85 SNJ54LV240AW SNJ54LV240AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV240AFK SNJ54LV240AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

    !"#$%&' #"'(' 

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+(*(%&&*.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

SN54LV240A ...J OR W PACKAGE

SN74LV240A . . . DB, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

1Y1

2A4

1Y2

2A3

1Y3

1A2

2Y3

1A3

2Y2

1A4

SN54LV240A . . . FK PACKAGE

(TOP VIEW)

2Y4

1A1

1OE

1Y4

2A2 2OE

2Y1

2A1

Summary of content (20 pages)

PAGE 1
SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.
PAGE 2
SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
PAGE 3
SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 4
SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005 recommended operating conditions (see Note 4) VCC VIH VI Input voltage VO Output voltage ∆t/∆v VCC = 2 V VCC = 2.3 V to 2.7 V High-level input voltage Low-level input voltage IOL SN74LV240A MIN MAX MIN MAX 2 5.5 2 5.5 Supply voltage VIL IOH SN54LV240A VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.
PAGE 5
SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tdis OE Y tpd A ten OE tdis OE PARAMETER LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX ∗ 6.3 11.6∗ temperature SN54LV240A range, SN74LV240A MIN 1∗ MAX 14∗ MIN MAX 1 14 8.5∗ 14.6∗ 1∗ 17∗ 1 17 9.7∗ 14.
PAGE 6
SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005 noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV240A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.56 V Quiet output, minimum dynamic VOL −0.49 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 2.82 V High-level dynamic input voltage 2.
PAGE 7
SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74LV240ADBR SSOP DB 20 2000 330.0 16.4 SN74LV240ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV240ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV240ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LV240ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LV240ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LV240ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LV240APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LV240APWR TSSOP PW 20 2000 367.0 367.0 38.
PAGE 13
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 14
PAGE 15
PAGE 16
PAGE 17
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PAGE 19
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.