Datasheet

 
  
  
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each multivibrator)
INPUTS
OUTPUTS
FUNCTION
CLR
A B Q Q
FUNCTION
L X X L H Reset
H HXLH Inhibit
H XLLH Inhibit
H L ↑ Outputs enabled
H ↓ H Outputs enabled
↑
†
L H Outputs enabled
†
This condition is true only if the output of the latch formed by the
NAND gate has been conditioned to the logic 1 state prior to CLR
going high. This latch is conditioned by taking either A high or B
low while CLR
is inactive (high).
logic diagram, each multivibrator (positive logic)
CLR
C
ext
R
ext
/C
ext
R
B
A
Q
Q
input/output timing diagram
A
B
CLR
Q
Q
t
w
t
w
R
ext
/C
ext
t
w