Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Master rest Differential TSSOP 16

 

  

 

SCLS400G − APRIL 1998 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 7.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D Contain Four Flip-Flops With Double-Rail

Outputs

D Applications Include:

− Buffer/Storage Registers

− Shift Registers

− Pattern Generators

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The ’LV175A devices are quadruple D-type

flip-flops designed for 2-V to 5.5-V V

operation.

These devices have a direct clear (CLR

) input and

feature complementary outputs from each

flip-flop.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − D

Tube of 40 SN74LV175AD

LV175A

SOIC − D

Reel of 2500 SN74LV175ADR

LV175A

SOP − NS Reel of 2000 SN74LV175ANSR 74LV175A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV175ADBR LV175A

−40°C to 85°C

Tube of 90 SN74LV175APW

TSSOP − PW

Reel of 2000 SN74LV175APWR

LV175A

TSSOP − PW

Reel of 250 SN74LV175APWT

LV175A

TVSOP − DGV Reel of 2000 SN74LV175ADGVR LV175A

CDIP − J Tube of 25 SNJ54LV175AJ SNJ54LV175AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV175AW SNJ54LV175AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV175AFK SNJ54LV175AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

SN54LV175A ...J OR W PACKAGE

SN74LV175A ...D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

SN54LV175A . . . FK PACKAGE

(TOP VIEW)

CLR

GND

CLK

3212019

910111213

CLR

CLK

GND

NC − No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

    !"#$% !%&% 

 %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# 

)$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/,

("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++

)&(&#$$(,

Summary of content (17 pages)

PAGE 1
SCLS400G − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.
PAGE 2
SCLS400G − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK.
PAGE 3
SCLS400G − APRIL 1998 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 4
SCLS400G − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV175A VCC Supply voltage VIH VCC = 2 V VCC = 2.3 V to 2.7 V High-level input voltage VIL Low-level input voltage VI VO Input voltage VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 5.5 MAX 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 UNIT V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.
PAGE 5
SCLS400G − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX CLR low tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ SN54LV175A MIN MAX SN74LV175A MIN 6 6 6 6.5 7 7 Data 7 7.5 7.5 CLR inactive 7 7.5 7.5 0.
PAGE 6
SCLS400G − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 3.3 V ± 0.
PAGE 7
SCLS400G − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC Timing Input 50% VCC 0V tw 50% VCC 50% VCC th tsu VCC Input S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Data Input VCC 50% VCC
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LV175ADGVR TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 12.0 Q1 DGV 16 2000 330.0 12.4 6.8 4.0 1.6 W Pin1 (mm) Quadrant SN74LV175ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV175ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV175ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV175ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV175ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV175APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV175APWT TSSOP PW 16 250 367.0 367.0 35.
PAGE 12
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 13
PAGE 14
PAGE 15
PAGE 16
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.