Datasheet

 
   
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
15
9
7
6
13
SH/LD
CLR
CLK
CLK INH
Q
H
234510111214
SER
ABCDEFGH
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
typical clear, shift, load, inhibit, and shift sequence
Clear Load
Inhibit
H
H
H
H
H
H HHHH
LLL
L
L
L
CLK
CLK INH
SER
A
B
C
D
E
F
G
H
SH/LD
CLR
Q
H
Parallel
Inputs
Serial Shift Serial Shift