Datasheet

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN54LV138A, SN74LV138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS395L – APRIL 1998 – REVISED AUGUST 2005
These devices are designed for high-performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory systems, these decoders can be used to minimize
the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the
delay times of these decoders and the enable time of the memory usually are less than the typical access time of
the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of
eight output lines. The two active-low ( G2A, G2B) and one active-high (G1) enable inputs reduce the need for
external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters
and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing
applications.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
ENABLE INPUTS SELECT INPUTS OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y20 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
X X H X X X H H H H H H H H
L X X X X X H H H H H H H H
H L L L L L L H H H H H H H
H L L L L H H L H H H H H H
H L L L H L H H L H H H H H
H L L L H H H H H L H H H H
H L L H L L H H H H L H H H
H L L H L H H H H H H L H H
H L L H H L H H H H H H L H
H L L H H H H H H H H H H L
2