Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74LV SOIC 14

SN54LV00A, SN74LV00A

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 6.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

SN54LV00A ...J OR W PACKAGE

SN74LV00A ...D, DB, DGV, NS,

OR PW PACKAGE

(TOP VIEW)

GND

3212019

910111213

SN54LV00A . . . FK PACKAGE

(TOP VIEW)

GND

NC − No internal connection

SN74LV00A . . . RGY PACKAGE

(TOP VIEW)

114

GND

description/ordering information

These quadruple 2-input positive-NAND gates are designed for 2-V to 5.5-V V

operation.

The ’LV00A devices perform the Boolean function Y = A

• B or Y = A + B in positive logic.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Reel of 1000 SN74LV00ARGYR LV00A

SOIC D

Tube of 50 SN74LV00AD

LV00A

SOIC − D

Reel of 2500 SN74LV00ADR

LV00A

SOP − NS Reel of 2000 SN74LV00ANSR 74LV00A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV00ADBR LV00A

40 C

85 C

Tube of 90 SN74LV00APW

TSSOP − PW

Reel of 2000 SN74LV00APWR

LV00A

TSSOP

Reel of 250 SN74LV00APWT

LV00A

TVSOP − DGV Reel of 2000 SN74LV00ADGVR LV00A

CDIP − J Tube of 25 SNJ54LV00AJ SNJ54LV00AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV00AW SNJ54LV00AW

LCCC - FK Tube of 55 SNJ54LV00AFK SNJ54LV00AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (21 pages)

PAGE 1
SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports SN54LV00A . . . J OR W PACKAGE SN74LV00A . . .
PAGE 2
SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 description/ordering information (continued) These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
PAGE 3
SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV00A VCC MIN MAX 2 5.5 Supply voltage VCC = 2 V VIH High level input voltage High-level 1.5 Low level input voltage Low-level VI Input voltage VO Output voltage VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 Input transition rise or fall rate TA Operating free-air temperature V V 0.5 0.5 VCC × 0.
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SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpdd A Y LOAD CAPACITANCE free-air TA = 25°C MIN temperature SN54LV00A range, SN74LV00A TYP MAX MIN MAX MIN MAX CL = 15 pF 7.1* 12.9* 1* 16* 1 15 CL = 50 pF 9.6 16.
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SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data In
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV00ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV00ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV00ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV00ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LV00ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LV00ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LV00ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LV00APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV00APWT TSSOP PW 14 250 367.0 367.0 35.
PAGE 11
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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