Datasheet

1
2
4
6
8
19
11
13
15
17
3
5
7
9
12
14
16
18
1A1
1A2
1A3
1A4
1Y1
2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
2G
1G
Copyright © 2016, Texas Instruments Incorporated
12
SN54LS240 , SN54LS241 , SN54LS244 , SN54S240 , SN54S241 , SN54S244
SN74LS240 , SN74LS241 , SN74LS244 , SN74S240 , SN74S241 , SN74S244
SDLS144D –APRIL 1985–REVISED OCTOBER 2016 www.ti.com
Product Folder Links: SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240
SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244
Submit Documentation Feedback Copyright © 1985–2016, Texas Instruments Incorporated
Pin numbers shown are for DB, DW, J, N, NS, and W packages
Figure 18. SNx4LS244 and SNx4S244
Logic Diagram
8.3 Feature Description
8.3.1 3-State Outputs
The 3-state outputs can drive bus lines directly. All outputs can be put into high impedance mode through the G
pin.
8.3.2 PNP Inputs
This device has PNP inputs which reduce dc loading on bus lines.
8.3.3 Hysteresis on Bus Inputs
The bus inputs have built-in hysteresis that improves noise margins.
8.4 Device Functional Modes
The SNx4LS24x and SNx4S24x devices can be used as inverting and non-inverting bus buffers for data line
transmission and can isolate input to output by setting the G pin HIGH. Table 1, Table 2, and Table 3 list the
function tables for all devices.
Table 1. SNx4LS240 and SNx4S240
Function Table
INPUTS OUTPUTS
G A Y
L L H
L H L
H X Z