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ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver PDIP 20

µ/6240, µ6240

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

On products compliant to MIL-PRF-38535, all parameters are

tested unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54LS240

SN54LS241

SN54LS244

SN54S240

SN54S241

SN54S244

SN74LS240

SN74LS241

SN74LS244

SN74S240

SN74S241

SN74S244

SDLS144D –APRIL 1985–REVISED OCTOBER 2016

SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features

• Inputs Tolerant Down to 2 V, Compatible With

3.3-V or 2.5-V Logic Inputs

• Maximum t

of 15 ns at 5 V

• 3-State Outputs Drive Bus Lines or Buffer Memory

Address Registers

• PNP Inputs Reduce DC Loading

• Hysteresis at Inputs Improves Noise Margins

2 Applications

• Servers

• LED Displays

• Network Switches

• Telecom Infrastructure

• Motor Drivers

• I/O Expanders

3 Description

The SNx4LS24x, SNx4S24x octal buffers and line

drivers are designed specifically to improve both the

performance and density of three-state memory

address drivers, clock drivers, and bus-oriented

receivers and transmitters. The designer has a choice

of selected combinations of inverting and non-

inverting outputs, symmetrical, active-low output-

control (G) inputs, and complementary output-control

(G and G) inputs. These devices feature high fan-out,

improved fan-in, and 400-mV noise margin. The

SN74LS24x and SN74S24x devices can be used to

drive terminated lines down to 133 Ω.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

SN54LS24x,

SN54S24x

CDIP (20) – J 24.20 mm × 6.92 mm

CFP (20) – W 7.02 mm × 13.72 mm

LCCC (20) – FK 8.89 mm × 8.89 mm

SN74LS240,

SN74LS244

SSOP (20) – DB 7.20 mm × 5.30 mm

SN74LS24x,

SN74S24x

SOIC (20) – DW 12.80 mm × 7.50 mm

PDIP (20) – N 24.33 mm × 6.35 mm

SN74LS24x SOP (20) – NS 7.80 mm × 12.60 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Logic Diagram (Positive Logic)

Summary of content (38 pages)

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Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs 1 Features 3 Description • The SNx4LS24x, SNx4S24x octal buffers and line drivers are designed specifically to improve both the performance and density of three-state memory add
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History.....................................................
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 www.ti.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Supply voltage, VCC (2) Input voltage, VI V 7 SNx4S24x 5.5 Storage temperature, Tstg (2) UNIT 7 SNx4LS24x Off-state output voltage (1) MAX –65 V 5.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 www.ti.com SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 6.4 Thermal Information THERMAL METRIC SN74LS240, SN74LS244 (1) SN74LS24x, SN74S24x SN74LS24x DB (SSOP) DW (SOIC) N (PDIP) NS (SOP) 20 PINS 20 PINS 20 PINS 20 PINS (2) (3) UNIT RθJA Junction-to-ambient thermal resistance 94.3 90.3 50.6 76.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 55.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 www.ti.com Electrical Characteristics – SNx4S24x (continued) over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP (2) MAX UNIT IOZH VCC = MAX, VIL = 0.8 V, VIH = 2 V, VO = 2.4 V 50 IOZL VCC = MAX, VIL = MAX, VIH = 2 V, VO = 0.5 V –50 µA II VCC = MAX, VI = 5.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 www.ti.com SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 6.9 Typical Characteristics VCC = 5 V, TA = 25°C, CL = 45 pF, and RL = 667 Ω (unless otherwise noted) 5.5 4.5 Voltage (V) 3.5 2.5 1.5 0.5 Input Output -0.5 0 5 10 Time (ns) 15 20 D001 Figure 1. Simulated Propagation Delay From Input to Output 7 Parameter Measurement Information 7.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 www.ti.com 3V 3V Timing Input Input 1.3 V 1.3 V 1.3 V 0V 0V th tsu Data Input tPLH 3V 1.3 V In-Phase Output (see Note D) 1.3 V 0V Figure 6. Voltage Waveforms, Setup and Hold Times tPHL VOH 1.3 V 1.3 V VOL tPHL Out-of-Phase Output (see Note D) tPLH VOH 1.3 V 1.3 V VOL Figure 7.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 www.ti.com SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 7.2 SN54S24x and SN74S24x Devices Test Point VCC High-Level Pulse 1.5 V RL From Output Under Test (see Note B) CL (see Note A) tw Low-Level Pulse 1.5 V 1.5 V 0V th tsu 3V Data Input RL From Output Under Test CL (see Note A) 3V Timing Input VCC Test Point 1.5 V 1.5 V 0V Figure 13.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 www.ti.com 3V Output Control (low-level enabling) 1.5 V 0V tPZL Waveform 1 (see Notes C and D) tPLZ ≈1.5 V 1.5 V VOL VOL + 0.5 V tPHZ tPZH Waveform 2 (see Notes C and D) 1.5 V VOH 1.5 V VOH − 0.5 V ≈1.5 V A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 www.ti.com SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 8 Detailed Description 8.1 Overview This device is organized as two 4-bit buffers and drivers with separate output-enable (G) inputs. When G is low, the device passes data from the A inputs to the Y outputs. When G is high, the outputs are in the high impedance state. Inputs can be driven from either 3.3-V or 5-V devices.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 www.ti.com 1 1G 1A1 1A2 1A3 1A4 2G 2A1 2A2 2A3 2A4 2 18 4 16 6 14 8 12 1Y1 1Y2 1Y3 1Y4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 Copyright © 2016, Texas Instruments Incorporated Pin numbers shown are for DB, DW, J, N, NS, and W packages Figure 18. SNx4LS244 and SNx4S244 Logic Diagram 8.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 www.ti.com SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 Table 2. SNx4LS241 and SNx4S241 Function Table CHANNEL 1 CHANNEL 2 INPUTS OUTPUT INPUTS OUTPUT 1G 1A 1Y 2G 2A 2Y L L L H L L L H H H H H H X Z L X Z Table 3.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 www.ti.com SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 Typical Application (continued) 9.2.3 Application Curve 0.5 0.4 VCC @ 4.75 V VOL (max) V 0.3 0.2 0.1 0 3 6 9 12 15 18 21 24 27 I OL (mA) Figure 23. VOL vs IOL 9.3 System Examples The SNx4LS240 and SNx4S240 devices can be used to buffer signals along a memory bus.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 www.ti.com System Examples (continued) 'LS240/'S240 From Data Bus Output Ports G Output-Port Control From Data Bus Input Ports G Input-Port Control Copyright © 2016, Texas Instruments Incorporated Figure 25.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 www.ti.com SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-µF bypass capacitor.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 www.ti.com 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4.
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 www.ti.com SDLS144D – APRIL 1985 – REVISED OCTOBER 2016 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LS240DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LS240DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LS240NSR SO NS 20 2000 330.0 24.4 9.0 13.0 2.4 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LS240DBR SN74LS240DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74LS240NSR SO NS 20 2000 367.0 367.0 45.0 SN74LS241DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LS241NSR SO NS 20 2000 367.0 367.0 45.0 SN74LS244DBR SSOP DB 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 20 1 13.0 12.6 NOTE 3 18X 1.27 2X 11.43 10 11 B 7.6 7.4 NOTE 4 20X 0.51 0.31 0.25 C A B 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.3 0.1 1.27 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
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EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7.
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EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 11 10 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.