Datasheet

   
  
  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
PHL
t
PLH
t
PLH
t
PHL
3 V
3 V
0 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
3 V
0 V
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
(see Note B)
V
CC
R
L
From Output
Under Test
C
L
= 15 pF
(see Note A)
Test
Point
NOTES: A. C
L
includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z
O
≈ 50 Ω and, for SN54/74221,
t
r
≤ 7 ns, t
f
≤ 7 ns, for SN54/74LS221, t
r
≤ 15 ns, t
f
≤ 6 ns.
E. All measurements are made between the 1.5-V points of the indicated transitions for the SN54/74221 or between the 1.3-V points
for the SN54/74LS221.
Figure 2. Load Circuits and Voltage Waveforms