Datasheet

SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, V
CC
= 5 V, T
A
= 25°C, R
L
= 667 Ω (see Figure 2)
PARAMETER
TEST CONDITIONS
SN54LS173A SN74LS173A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
f
max
Maximum clock frequency 30 50 30 50 MHz
t
PHL
Propagation delay time,
high-to-low-level output from clear input
26 35 26 35 ns
t
PLH
Propagation delay time,
low-to-high-level output from clock input
C
L
= 45 pF
17 25 17 25
ns
t
PHL
Propagation delay time,
high-to-low-level output from clock input
L
22 30 22 30
ns
t
PZH
Output enable time to high level 15 23 15 23
ns
t
PZL
Output enable time to low level 18 27 18 27
ns
t
PHZ
Output disable time from high level
C
L
=5
p
F
11 20 11 20
ns
t
PLZ
Output disable time from low level
C
L
=
5
pF
11 17 11 17
ns