Datasheet

SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, V
CC
= 5 V, T
A
= 25°C, R
L
= 400 Ω (see Figure 1)
PARAMETER
TEST CONDITIONS
SN54173 SN74173
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
f
max
Maximum clock frequency 25 35 25 35 MHz
t
PHL
Propagation delay time,
high-to-low-level output from clear input
18 27 18 27 ns
t
PLH
Propagation delay time,
low-to-high-level output from clock input
C
L
= 50 pF
28 43 28 43
ns
t
PHL
Propagation delay time,
high-to-low-level output from clock input
L
19 31 19 31
ns
t
PZH
Output enable time to high level 7 16 30 7 16 30
ns
t
PZL
Output enable time to low level 7 21 30 7 21 30
ns
t
PHZ
Output disable time from high level
C
L
=5
p
F
3 5 14 3 5 14
ns
t
PLZ
Output disable time from low level
C
L
=
5
pF
3 11 20 3 11 20
ns