Datasheet

   
    
        
SDLS053B − OCTOBER 1976 − REVISED MAY 2004
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is
encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.
The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been provided to allow octal expansion without the need for external
circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent
one normalized Series 54/74 or 54/74LS load, respectively.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube SN74LS148N SN74LS148N
0°C to 70°C
SOIC − D
Tube SN74LS148D
LS148
0°C to 70°C SOIC − D
Tape and reel SN74LS148DR
LS148
SOP − NS Tape and reel SN74LS148NSR 74LS148
CDIP − J Tube SNJ54LS148J SNJ54LS148J
−55°C to 125°C
CFP − W Tube SNJ54LS148W SNJ54LS148W
−55 C to 125 C
LCCC − FK Tube SNJ54LS148FK SNJ54LS148FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE − ’147, ’LS147
INPUTS
OUTPUTS
1 2 3 4 5 6 7 8 9 D C B A
H H H H H H H H H H H H H
X XXXXXXXLLHHL
X XXXXXXLHLHHH
X XXXXXLHHHLLL
X XXXXLHHHHLLH
X XXXLHHHHHLHL
X XXLHHHHHHLHH
X XLHHHHHHHHLL
X LHHHHHHHHHLH
L H H H H H H H H H H H L
H = high logic level, L = low logic level, X = irrelevant