Datasheet

V
CC
Unused Input
Input
Output Output
Input
Unused Input
17
18
19
20
21
22
4.5 4.7 4.9 5.1 5.3 5.5
t
pd
(ns)
V
CC
(V)
C001
11
SN54HCT244 , SN74HCT244
www.ti.com SCLS175E –MONTH 2003–REVISED AUGUST 2016
Product Folder Links: SN54HCT244 SN74HCT244
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Typical Application (continued)
9.2.3 Application Curve
Figure 5. Propagation Delay vs V
CC
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each V
CC
terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-µF capacitor. If there are multiple V
CC
terminals, then TI recommends 0.01-µF or
0.022-µF capacitors for each power terminal. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The
bypass capacitor must be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input and gate are used, or
when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
V
CC
, whichever makes more sense or is more convenient.
11.2 Layout Example
Figure 6. Layout Diagram