Datasheet

 
  
  
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
V
CC
T
A
= 25°C SN54HC594 SN74HC594
UNIT
V
CC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 5 3.3 4
f
clock
Clock frequency
4.5 V
25 17 20
MHz
f
clock
Clock frequency
6 V 29 20 24
MHz
2 V 100 150 125
SRCLK or RCLK high or low
4.5 V 20 30 25
t
w
Pulse duration
SRCLK or RCLK high or low
6 V 17 25 21
ns
t
w
Pulse duration
2 V 100 150 125
ns
SRCLR or RCLR low
4.5 V 20 30 25
SRCLR or RCLR low
6 V 17 25 21
2 V 90 135 110
SER before SRCLK↑
4.5 V 18 27 22
SER before SRCLK↑
6 V 15 23 19
2 V 90 135 110
SRCLK↑ before RCLK↑
†
4.5 V 18 27 22
SRCLK↑ before RCLK↑
†
6 V 15 23 19
2 V 50 75 63
t
su
Setup time SRCLR low before RCLK↑
4.5 V 10 15 13
ns
t
su
Setup time
SRCLR low before RCLK↑
6 V 9 13 11
ns
2 V 20 20 20
SRCLR high (inactive) before SRCLK↑
4.5 V 10 10 10
SRCLR high (inactive) before SRCLK↑
6 V 10 10 10
2 V 5 5 5
RCLR high (inactive) before SRCLK↑
4.5 V 5 5 5
RCLR high (inactive) before SRCLK↑
6 V 5 5 5
2 V 5 5 5
t
h
Hold time, SER after SRCLK↑
4.5 V
5 5 5
ns
t
h
Hold time, SER after SRCLK
6 V 5 5 5
ns
†
This setup time ensures that the output register receives stable data from the shift-register outputs. The clocks may be tied together, in which
case the output register is one clock pulse behind the shift register.
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