Datasheet

 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
V
CC
T
A
= 25°C SN54HC590A SN74HC590A
UNIT
V
CC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 4 2.5 3.2
f
clock
Clock frequency
4.5 V
20 13 16
MHz
f
clock
Clock frequency
6 V 24 16 19
MHz
2 V 125 200 155
CCLK or RCLK high or low
4.5 V 25 38 31
t
w
Pulse duration
CCLK or RCLK high or low
6 V 21 32 26
ns
t
w
Pulse duration
2 V 100 150 125
ns
CCLR low
4.5 V 20 30 25
CCLR low
6 V 17 26 21
2 V 100 150 125
CCKEN low before CCLK↑
4.5 V 20 30 25
CCKEN low before CCLK↑
6 V 17 26 21
2 V 100 150 125
t
su
Setup time CCLR high (inactive) before CCLK↑
4.5 V 20 30 25
ns
t
su
Setup time
CCLR high (inactive) before CCLK↑
6 V 17 26 21
ns
2 V 100 150 125
CCLK↑ before RCLK↑
†
4.5 V 20 30 25
CCLK↑ before RCLK↑
†
6 V 17 26 21
2 V 50 75 60
t
h
Hold time CCKEN low after CCLK↑
4.5 V 10 15 12
ns
t
h
Hold time
CCKEN low after CCLK
6 V 9 13 11
ns
†
This setup time ensures that the register gets stable data from the counter outputs. The clocks may be tied together, in which case the register
is one clock pulse behind the counter.