Datasheet
SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding
clear (CLR
) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high,
SH/LD
enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock
(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on
the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR
overrides all other inputs, including CLK, and resets all flip-flops to zero.
FUNCTION TABLE
INPUTS
OUTPUTS
INPUTS
INTERNAL
CLR SH/LD
CLK INH CLK SER
PARALLEL
A...H
Q
A
Q
B
Q
H
L X X X X X L L L
H XLLX XQ
A0
Q
B0
Q
H0
H LL↑ X a...h a bh
H HL↑ HXHQ
An
Q
Gn
H HL↑ LXLQ
An
Q
Gn
H X H ↑ X X Q
A0
Q
B0
Q
H0
logic diagram (positive logic)
1D
C1
15
9
7
6
13
SH/LD
CLR
CLK
CLK INH
Q
H
234510111214
SER
ABCDEFGH
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.