Datasheet


   
SCLS473A − APRIL 2003 − REVISED JANUARY 2004
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
SH/LD
CLK CLK INH
FUNCTION
L X X Parallel load
H H X No change
H X H No change
H L ↑ Shift
†
H ↑ L Shift
†
†
Shift = content of each internal register shifts
toward serial output Q
H
. Data at SER is
shifted into the first register.
logic diagram (positive logic)
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
Q
H
Q
H
11 12 13 14 3 4 5 6
ABCDEFGH