Datasheet

SN54HC165, SN74HC165
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116F − DECEMBER 1982 − REVISED DECEMBER 2010
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
V
T
A
= 25°C SN54HC165 SN74HC165
UNIT
V
CC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 6 4.2 5
f
clock
Clock frequency
4.5 V 31 21 25
MHz
f
clock
Clock frequency
6 V 36 25 29
MHz
2 V 80 120 100
SH/LD low
4.5 V 16 24 20
t
Pulse duration
SH/LD low
6 V 14 20 17
ns
t
w
Pulse duration
2 V 80 120 100
ns
CLK high or low
4.5 V 16 24 20
CLK high or low
6 V 14 20 17
2 V 80 120 100
SH/LD high before CLK↑
4.5 V 16 24 20
SH/LD high before CLK↑
6 V 14 20 17
2 V 40 60 50
SER before CLK↑
4.5 V 8 12 10
SER before CLK↑
6 V 7 10 9
2 V 100 150 125
t
su
Setup time CLK INH low before CLK↑
4.5 V 20 30 25
ns
t
su
Setup time
CLK INH low before CLK↑
6 V 17 25 21
ns
2 V 40 60 50
CLK INH high before CLK↑
4.5 V 8 12 10
CLK INH high before CLK↑
6 V 7 10 9
2 V 100 150 125
Data before SH/LD↓
4.5 V 20 30 25
Data before SH/LD↓
6 V 17 26 21
2 V 5 5 5
SER data after CLK↑
4.5 V 5 5 5
t
Hold time
SER data after CLK↑
6 V 5 5 5
ns
t
h
Hold time
2 V 5 5 5
ns
PAR data after SH/LD↓ 4.5 V 5 5 5
/
6 V 5 5 5