Datasheet

SN54HC165, SN74HC165
8-BIT PARALLEL-LOAD SHIFT REGISTERS
SCLS116F − DECEMBER 1982 − REVISED DECEMBER 2010
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
FUNCTION TABLE
INPUTS
FUNCTION
SH/LD
CLK CLK INH
FUNCTION
L X X Parallel load
H H X No change
H X H No change
H L ↑ Shift
†
H ↑ L Shift
†
†
Shift = content of each internal register shifts
toward serial output Q
H
. Data at SER is
shifted into the first register.
logic diagram (positive logic)
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
Q
H
Q
H
11 12 13 14 3 4 5 6
ABCDEFGH
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.